1. Field of the Invention
The present invention relates to a semiconductor memory which has volatile memory cells having capacitors and has an SRAM interface.
2. Description of the Related Art
Recently, mobile devices such as a cellular phone have been sophisticated in service facilities, and the amounts of data to be handled continue growing. Then, higher capacities are required of the work memories to be mounted on the mobile devices accordingly.
Conventionally, the work memories of the mobile devices have used SRAMs which allow easy system configuration. The SRAMs are, however, greater than DRAMs in the number of devices for constituting each single bit of cell, and thus are disadvantageous for higher capacities. On this account, semiconductor memories referred to as pseudo SRAMs, having both the high capacities of DRAMs and the usability of SRAMs, have been developed.
The pseudo SRAMs have DRAM memory cells and SRAM interfaces. An overview of a pseudo SRAM is disclosed, for example, in U.S. Pat. No. 6,392,958.
Since the pseudo SRAMs have DRAM memory cores, the memory cells must be rewritten to avoid data crash after data read. Consequently, in a read operation, if a word line is selected and a different address signal is supplied to select another word line, the rewrite fails to be performed properly and the data in the memory cells crashes. That is, the pseudo SRAM malfunctions. In contrast, since SRAM memory cells are made of latches, the data in the memory cells will not crash even if a read operation is interrupted by the supply of another address signal during the read operation.
To avoid the foregoing malfunction, pseudo SRAMs have the timing specification that disables such a change in the address signal as reselects word lines during a read cycle.
The pseudo SRAMs have SRAM interfaces, and are basically compatible with SRAMs. As compared to SRAMs, however, there are some restrictions such as the timing specification as to the address change mentioned above. Thus, when the SRAMs mounted on systems are replaced with the pseudo SRAMs, the controllers for controlling the memories sometimes require modification.
Meanwhile, when a pseudo SRAM has 16 bits of I/O terminals (two bytes), external terminals for inputting a lower byte signal /LB and an upper byte signal /UB are typically formed so that data is input/output in units of a single byte. When lower eight bits of data are written to the memory cells or read from the memory cells, the lower byte signal /LB is enabled. When upper eight bits of data are written to the memory cells or read from the memory cells, the upper byte signal /UB is enabled. The product specifications on the pseudo SRAMs of this type are described, for example, in the data sheet of μPD4632312-X, a pseudo SRAM from NEC Corporation.
Nevertheless, while the pseudo SRAMs of this type can input and output data in units of bytes, the memory cores operate in response to 16 bits of data. Thus, for example, in writing lower 1-byte data alone to a memory core, upper 1-byte data must be masked from being written to the memory core. In addition, if the enable periods of the lower byte signal /LB and the upper byte signal /UB overlap in part, the write operation to the memory core must be started in time with the signal of slower disable timing between the lower byte signal /LB and the upper byte signal /UB.
As above, the conventional pseudo SRAMs of 16-bit configuration require a circuit for controlling the data mask and a circuit for controlling the start of a write operation (write wait circuit) for the sake of byte write. This has grown the control circuits in scale, producing the problem of greater chip size. In addition, the complicated write control at the time of byte write decreases the timing margin.